My Brain or Your Brain
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My Brain or Your Brain
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Digital Logic Stuffs
Clock Domain Crossing
Closed-Loop Solution — Sampling Signals with Synchronizers
MCP Formulation Using a Synchronized Enable Pulse
MCP Formulation with Feedback
Mean Time Before Failure
Metastability Propagation
Metastability
Multi-Cycle Path (MCP) formulation
Open-Loop Solution — Sampling Signals with Synchronizers
Passing Multiple Signals Between Clock Domains
Problem — Two Control Signals Crossing Together
Problem — Two Phase-Shifted Sequencing Control Signals
Synchronizing Signals from the Sending Clock Domain
Three Edge Requirement
Two flip-flop synchronizer
Protocols
MIPI PHY D
Architecture
Clock Lane, Data Lanes, and the PHY-Protocol Interface
Clock Lane
Data Lane Types
High-Frequency Clock Generation
Lane Module Types
Lane Modules
Lane Symbol Macros and Symbols Legend
Master and Slave
Selectable Lane Options
Unidirectional PHY Configurations
D-PHY Overview
PHY Functionality
PCI, PCI-x, PCIe
PCI
Direct Memory Access (DMA)
Example of PCI Bus Cycle
PCI Address Space Map
PCI Configuration Cycle Generation
PCI Disconnect Protocol
PCI Error Handling
PCI Function Configuration Register Space
PCI Interrupt Handling
PCI Retry Protocol
PCI Transaction Models
Peer-to-Peer Transfers in PCI
Programmed IO (PIO)
Reflected-Wave Signalling
PCI-X
Attribute Phase
Message Signaled Interrupts
PCI-X 2.0 Source-Synchronous Delivery
PCI-X Improvements Over PCI
PCI-X Split Transaction Solution
PCI-X Transaction Characteristics
Problems with the Common Clock Approach of PCI and PCI-X 1.0 Parallel Bus Model
PCIe
Data Link Layer
Ack & Nak Protocol
Data Link Layer
DLLP
Physical Layer
AC-coupled Link
Link Training
Physical Layer - Logical
Transaction Layer
IO & Config Writes
PCIe Flow Control
PCIe Locked Read
PCIe Ordinary Memory Read
PCIe Posted Writes
PCIe Quality of Service
PCIe Transaction Ordering
TLP
Transaction Layer
Device Core (Software Layer)
Differential Signaling
Example of PCIe System
Introduction to PCI Express
PCIe Backward Compatibility
PCIe Packet Travels Overview
PCIe Serial Transaction
PCIe Software Compatibility
PCIe Source-Synchronous Clock
PCIe Topology
PCIe’s Layered Architecture
SPI
PICmicro
PIC Microcontrollers Control & Status Registers
Interrupts in SPI Communication
Introduction to SPI
SPI Bus Topologies
SPI Clock Polarity (CPOL) & Phase (CPHA)
SPI Communication Process
SPI Modes
USB 3.0
End-to-End Protocols (USB SuperSpeed)
Port-to-Port Protocols (USB SuperSpeed)
Protocols Improvements Compared to USB 2.0
USB 3.0 Host Controllers
System Verilog
Associative Arrays
Controlling Timing of Synchronous Signals with a Clocking Block
Fixed-Size Arrays
Mailbox in a Testbench
Queues
Semaphores
Stimulus Timing
Threads in SystemVerilog Testbenches
Timing Problems in Verilog
Doctor Strange
Ferulic Acid Ameliorates Alzheimer’s Disease‑like Pathology and Repairs Cognitive Decline by Preventing Capillary Hypofunction in APP PS1 Mice
Verilog and Logic Circuit Design
Example Circuit Design
4 Bit Priority Encoder
4-bit Adder and Subtractor
4-Bit Binary Multiplier
4-Bit Carry-Lookahead Adder
4-Bit Ripple-Carry Adder
8 Bit Priority Encoder
16-Bit Adder with Register File
Accumulator
Carry-Lookahead Generator
D Flip Flop
D Latch
Debounce Circuit
Decoder 3 to 8
Frequency Divider
Full Adder
Mearly Machine
Multiplier Unit
Parallel In Shift Register
Serial In Shift Register
Traffic Light
Basic structure of Verilog and Circuit Design
Binary Multiplication
Blocking and Non-blocking Assignments
Declaring Numbers in Verilog
Finite State Machine
Mealy Machine
Moore Machine
Two's Complement and Signed Numbers Subtraction
Enter to select
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  • Traffic Class (TC) Field (3-bit)

    • Every PCIe TLP (Transaction Layer Packet) includes a 3-bit Traffic Class field.
    • Software sets this when creating a transaction.
    • Higher TC = higher priority (though the actual priority scheme is implementation dependent).

  • Virtual Channels (VCs)

    • Each physical PCIe port contains multiple logical buffers — one per VC.
    • Packets are sorted into the right VC based on their TC.
    • Think of this as “priority queues” per link.

  • VC Arbitration Logic

    • Since a port may have packets waiting in multiple VCs, the port needs arbitration logic to decide which VC gets to transmit next.
    • This can be a simple priority scheme (always serve VC0 first, then VC1, etc.) or a programmable policy like weighted round-robin.

  • Port Arbitration (Switch Fabric Level)

    • If multiple input ports on a switch want to send data to the same output port, the switch needs to decide who wins.
    • Again, this can be based on VC priority and fairness mechanisms.

  • End Goal: Deterministic Bandwidth & Latency

    • With all of the above, the system can guarantee that certain streams (like video) have enough bandwidth and low enough latency to work properly.
    • Other streams (like SCSI storage) will still be delivered, just not necessarily as quickly.
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